This invention relates to a digital adder.
Digital adders include serial adders and parallel adders. With the serial adder, the product between the number of data bits and the number of times of data processings becomes a clock rate, and the processing of data at a bit rate higher than the clock rate cannot be realized. In such case, the parallel adder is employed. With the parallel adder, however, that number of full adders which is equal to the number of data bits are required, and the number of constituent elements increases. Another problem is that, since an operation must be completed within one clock period, carry needs to be executed at high speed.